1. Field of the Invention
The present invention relates generally to electrical circuit design, and more particularly but not exclusively to techniques for verifying the design of an integrated circuit.
2. Description of the Background Art
Integrated circuits are typically designed using software referred to as “IC design tools.” IC design tools are available for schematic entry, simulation, layout creation, and verification. An integrated circuit design process may include an engineer creating a circuit schematic. A circuit schematic is a diagram depicting the components of the design and the wires connecting the components. A netlist, which is a listing of the components and wires of the design, may be generated from the circuit schematic.
A circuit layout is a diagram depicting physical representations of components and wires as they will be fabricated into an integrated circuit. To verify that a layout is consistent with its corresponding circuit schematic, a netlist listing the components and wires in the layout may be generated and compared to a netlist of the circuit schematic. The just mentioned verification process is referred to as an LVS (layout versus schematic) verification. From the layout, masks for fabricating an integrated circuit may be created.
A piece of wire connecting devices or points in an integrated circuit has associated capacitance, resistance, and inductance that are also referred to as “parasitics.” Parasitics are affected by various factors including the wire's dimensions, material, routing, and load. As integrated circuit dimensions get smaller and signals get faster, the effects of parasitics on circuit performance become more significant. Using an IC design tool, parasitics may be extracted from the layout, and then incorporated into the circuit schematic using a process referred to as “back-annotation”. The back-annotated circuit schematic may then be simulated to check if the resulting parasitics are within design constraints.
In some applications, such as custom integrated circuit design, the back-annotation process results in a lot of unexpected parasitics. In these applications, instead of back-annotating, a simulation schematic depicting hand-drawn estimates of the parasitics is created from the circuit schematic. To check if the layout meets design guidelines or if the simulation schematic can be relied on, a net extracted from a layout is compared to the same net extracted from the simulation schematic. One problem with this approach is that a netlist of the layout may be difficult to compare to a netlist of the simulation schematic. Another problem with this approach is that it is prone to schematic entry errors when a wire has several entry and exit points.